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PLATFORM ?= "xilinx_u250_xdma_201830_2"
XO_INPUT=../compile/resnet50.xo
KERNEL = resnet50
XCLBIN_OUTPUT=$(KERNEL).xclbin
XCLBIN_FREQ_MHZ ?= 250
XCLBIN_FREQ_OPTS := "0:$(XCLBIN_FREQ_MHZ)|1:$(XCLBIN_FREQ_MHZ)"
XCLBIN_OPTIMIZE := 2
#configuration defines passed to the HLS code
#can define chipscope core insertion during XOCC link
#example to add debug cores to all interfaces:
#CHIPSCOPE=--dk chipscope:$(KERNEL)_1:s_axi_control --dk chipscope:$(KERNEL)_1:m_axi_gmem0 --dk chipscope:$(KERNEL)_1:m_axi_gmem1
CHIPSCOPE=
#optional memory bank assignment, for multi-MM designs (MULTIBANK defined)
MEMBANK=
#example dual bank assignment:
#MEMBANK=--sp $(KERNEL)_1.gmem0:bank2 --sp $(KERNEL)_1.gmem1:bank3
#floorplanning
FLOORPLAN=`pwd`/floorplan.tcl
FLOORPLAN_OPTS=--xp vivado_prop:run.impl_1.STEPS.OPT_DESIGN.TCL.POST=$(FLOORPLAN)
#profiling
#example to add profiling to all kernels
#PROFILE_OPTS=--profile_kernel data:all:all:all
PROFILE_OPTS=

all: $(XCLBIN_OUTPUT)

$(XCLBIN_OUTPUT): $(XO_INPUT)
	v++ --link --target hw $(PROFILE_OPTS) --kernel_frequency $(XCLBIN_FREQ_OPTS) --save-temps -R2 --optimize $(XCLBIN_OPTIMIZE) $(CHIPSCOPE) $(MEMBANK) --platform $(PLATFORM) $(FLOORPLAN_OPTS) $< -o $@

.PHONY=clean
clean:
	-git clean -xfd
